Semiconductor device

ABSTRACT

According to one embodiment, a semiconductor device comprises a first nitride semiconductor layer on a substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a larger bandgap than the first nitride semiconductor layer. Source and drain electrodes are on the second nitride semiconductor layer. A gate electrode is between the source electrode and the drain electrode. A third nitride semiconductor layer of p-type conductivity is on the second nitride semiconductor layer between the drain electrode and the gate electrode and spaced from the drain electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-173396, filed Sep. 18, 2018, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device.

BACKGROUND

A low ON-state resistance and a high breakdown voltage are both preferred for a switching device used in, for example, an inverter circuit and power source switching. Silicon is mainly used as a semiconductor material for these switching devices, but the limits of silicon for achieving a lower ON-state resistance and a higher breakdown voltage are approaching or have already been reached. To improve the breakdown voltage and decrease the ON-state resistance to further degrees, it is considered necessary to change the semiconductor material. Use of nitride semiconductor materials, such as GaN and AlGaN, improves the trade-off relationship between ON-state resistance and breakdown voltage, which are largely dependent on the semiconductor material being used.

In the operation of a switching device, an ON state and an OFF state are repeatedly switched back and forth. In the OFF state, a high voltage is applied across a source electrode and a drain electrode. At this time, a depletion layer extends from a gate electrode toward the drain electrode. When the depletion layer reaches the drain electrode a state called “punch-through” is entered and the depletion layer stops extending. This drastically changes capacitance, which unfortunately causes current oscillation. At a portion where the drain electrode overlaps a surface protection film, electrons are trapped at an interface between the nitride semiconductor material and the surface protection film or within the surface protection film to unfavorably increase the ON-state resistance.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to another example of the first embodiment.

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a second embodiment.

FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another example of the second embodiment.

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a third embodiment.

FIG. 6 is a schematic cross-sectional view of a semiconductor device according to another example of the third embodiment.

DETAILED DESCRIPTION

Example embodiments provide a semiconductor device that prevents current oscillation from occurring during switching and prevents the trapping of electrons from increasing the ON-state resistance.

In general, according to one embodiment, a semiconductor device includes a first nitride semiconductor layer on a substrate and a second nitride semiconductor layer on the first nitride semiconductor layer. The second nitride semiconductor layer has a larger bandgap than the first nitride semiconductor layer.

Source and drain electrodes are on the second nitride semiconductor layer. A gate electrode is between the source electrode and the drain electrode. A third nitride semiconductor layer of p-type conductivity is on the second nitride semiconductor layer between the drain electrode and the gate electrode and is spaced from the drain electrode.

Example embodiments will now be described with reference to the accompanying drawings. In the drawings, identical or corresponding elements are given the same reference numerals.

In this disclosure, “nitride semiconductors” will generally refer to gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN) based semiconductors and other semiconductors materials including intermediate compositions of GaN, AlN, and InN.

In this specification, corresponding elements and the like are given the same reference numerals and description of such elements may not be made repeatedly.

In this specification, to indicate positional relationships among components, an upward direction of each drawing will be referred to as “upper”, and a downward direction of each drawing will be referred to as “lower”. In this specification, concepts of the terms “upper” and “lower” do not necessarily concern the gravity direction.

First Embodiment

A semiconductor device according to a first embodiment includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer, a source electrode disposed on the second nitride semiconductor layer, a drain electrode disposed on the second nitride semiconductor layer, a gate electrode disposed between the source electrode and the drain electrode, and a third nitride semiconductor layer of p-type conductivity disposed on the second nitride semiconductor layer between the drain electrode and the gate electrode and spaced from the drain electrode.

FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 a according to the first embodiment. The semiconductor device 100 a according to this embodiment is a high electron mobility transistor (HEMT) of nitride semiconductor.

The semiconductor device 100 a includes a substrate 2, a buffer layer 4, a first nitride semiconductor layer 6, a second nitride semiconductor layer 8, a third nitride semiconductor layer 10, an insulating film 20, a source electrode 30, a drain electrode 32, and a gate electrode 34.

As the substrate 2, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a sapphire (Al₂O₃) substrate is preferably used.

The first nitride semiconductor layer 6 is disposed on the substrate 2. The first nitride semiconductor layer 6 is made of, for example, undoped Al_(X)Ga_(1-X)N (0≤X<1). More specifically, examples include undoped GaN. The first nitride semiconductor layer 6 has a thickness of, for example, between 0.5 μm and 3 μm.

The second nitride semiconductor layer 8 is disposed on the first nitride semiconductor layer 6 and has a larger bandgap than the first nitride semiconductor layer 6. The second nitride semiconductor layer 8 is made of, for example, undoped Al_(Y)Ga_(1-Y)N (0<Y≤1, X<Y). The second nitride semiconductor layer 8 has a thickness t₁ of, for example, 15 nm to 50 nm.

A two-dimensional electron gas (hereinafter referred to as 2DEG) is generated at a hetero-bond interface between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8.

The buffer layer 4 is disposed between the substrate 2 and the first nitride semiconductor layer 6. The buffer layer 4 serves to reduce lattice mismatch between the substrate 2 and the first nitride semiconductor layer 6. The buffer layer 4 has, for example, a multilayer structure of aluminum gallium nitride (Al_(W)Ga_(1-W)N (0<W<1)).

The source electrode 30 is disposed on the second nitride semiconductor layer 8.

The drain electrode 32 is disposed on the second nitride semiconductor layer 8.

The source electrode 30 and the drain electrode 32 are preferably in ohmic contact with the second nitride semiconductor layer 8. A distance between the source electrode 30 and the drain electrode 32 is, for example, 5 μm or more and 30 μm or less.

The gate electrode 34 is disposed between the source electrode 30 and the drain electrode 32. The semiconductor device 100 a illustrated in FIG. 1 has what is referred to as a trench structure. In other words, the portion of the second nitride semiconductor layer 8 between the gate electrode 34 and the first nitride semiconductor layer 6 is removed, and the gate electrode 34 is extended into part of the first nitride semiconductor layer 6. With this structure, 2DEG is not generated right under the gate electrode 34. Consequently, the semiconductor device 100 a is what is called a normally-off semiconductor device. It is noted that the gate electrode 34 is not limited to the structure illustrated in FIG. 1 but may have a structure in which, for example, part of the second nitride semiconductor layer 8 remains between the gate electrode 34 and the first nitride semiconductor layer 6.

The source electrode 30, the drain electrode 32, and the gate electrode 34 are metal electrodes of, for example, a stacked structure of titanium (Ti) and aluminum (Al) or a stacked structure of nickel (Ni) and gold (Au).

The third nitride semiconductor layer 10 is disposed on the second nitride semiconductor layer 8 between the drain electrode 32 and the gate electrode 34 and spaced from the drain electrode 32. The third nitride semiconductor layer 10 has p-type conductivity. The third nitride semiconductor layer 10 contains magnesium (Mg), beryllium (Be), carbon (C) or zinc (Zn) as a p-type impurity. Preferably, the p-type impurity in the third nitride semiconductor layer 10 has a concentration in a range of 10¹⁹ cm⁻³ to 10²¹ cm⁻³, in which the third nitride semiconductor layer material has a Fermi level close to the valence band and has a crystallinity not significantly deteriorated.

Because the third nitride semiconductor layer 10 has p-type conductivity, the third nitride semiconductor layer 10 functions to lower a Fermi level in the vicinity of an interface between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8 below the third nitride semiconductor layer 10 so as to decrease a 2DEG concentration. Consequently, a first 2DEG portion of a relatively low concentration is formed in the vicinity of the interface between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8 below the third nitride semiconductor layer 10. On the right side of an area where the first 2DEG portion is formed in FIG. 1, a second 2DEG portion of a relatively high concentration is formed.

Preferably, a distance d₁ between the drain electrode 32 and the gate electrode 34 and a length d₂ of the third nitride semiconductor layer 10 in a direction parallel to a plane of the substrate 2 have a difference in a range represented by 0.5 μm≤d₁−d₂≤2 μm. The device is designed to have a breakdown voltage at such a value that the depletion layer extends as long as the length d₂. The 2DEG concentration in an area where the depletion layer exceeds the length d₂ (i.e., the second 2DEG portion) is increased to prevent the depletion layer from further extending from this area. This prevents punch-through to the drain electrode 32 and smooths any change in capacitance. When the difference d₁−d₂ (i.e., the second 2DEG portion) is too long, dimensions of the device become too large, and when the difference d₁−d₂ is too short, the effect of preventing the punch-through is too small. In view of this, preferably, the difference d₁−d₂ is in the above-mentioned range.

Preferably, the third nitride semiconductor layer 10 has a thickness t₂ of 40 nm or less so as to not to make the 2DEG concentration in the first 2DEG portion too low. Supposing that the third nitride semiconductor layer 10 is prepared to have the above-mentioned concentration, then if the thickness t₂ exceeds 40 nm and the thickness t₁ is in the above-mentioned range, the concentration of 2DEG induced below (in the first 2DEG portion) is drastically decreased to sharply increase the resistance in this portion. This results in an increase in ON-state resistance of the device, thereby degrading properties of the device. In view of this, the thickness t₂ of the third nitride semiconductor layer 10 is preferably 40 nm or less.

The insulating film 20 is disposed on the second nitride semiconductor layer 8. The insulating film 20 is a surface protection film to protect the nitride semiconductor material. In the semiconductor device 100 a illustrated in FIG. 1, part of the insulating film 20 also serves as a gate insulating film.

In FIG. 1, part of the source electrode 30 is in direct contact with the second nitride semiconductor layer 8. Between the gate electrode 34 and a portion where the source electrode 30 is in direct contact with the second nitride semiconductor layer 8, the insulating film 20 is disposed in a portion between the second nitride semiconductor layer 8 and the source electrode 30. This structure protects an upper surface of the second nitride semiconductor layer 8 in the vicinity of the source electrode 30.

The insulating film 20 is disposed between the gate electrode 34 and the second nitride semiconductor layer 8 and between the gate electrode 34 and the first nitride semiconductor layer 6.

Between the drain electrode 32 and the gate electrode 34, the insulating film 20 is formed to cover the third nitride semiconductor layer 10.

Part of the drain electrode 32 is in direct contact with the second nitride semiconductor layer 8. Between the gate electrode 34 and a portion where the drain electrode 32 is in direct contact with the second nitride semiconductor layer 8, the insulating film 20 is disposed in a portion between the second nitride semiconductor layer 8 and the drain electrode 32. This structure protects the upper surface of the second nitride semiconductor layer 8 in the vicinity of the drain electrode 32.

The insulating film 20 contains, for example, silicon nitride (SiN) or silicon oxide (SiO₂).

FIG. 2 is a schematic cross-sectional view of a semiconductor device 100 b according to another example of the first embodiment. The semiconductor device 100 b has no trench structure. In the semiconductor device 100 b, a p-type cap layer 36 is disposed between the gate electrode 34 and the second nitride semiconductor layer 8. The cap layer 36 is in direct contact with the third nitride semiconductor layer 10.

The cap layer 36 functions to lower a Fermi level in the vicinity of the interface between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8 below the cap layer 36 to make the 2DEG disappear, thus causing the semiconductor device 100 b to be normally off. The cap layer 36 is a nitride semiconductor material containing magnesium (Mg), beryllium (Be), carbon (C) or zinc (Zn) as a p-type impurity. Preferably, the p-type impurity in the cap layer 36 has a concentration of 10¹⁹ cm⁻³ or more and 10²¹ cm⁻³ or less. In some examples, the cap layer 36 and the third nitride semiconductor layer 10 may comprise the same material type.

Next, functions and effects of this first embodiment will be described.

In this first embodiment, the third nitride semiconductor layer 10 of p-type conductivity is disposed on the second nitride semiconductor layer 8 between the drain electrode 32 and the gate electrode 34 and spaced from the drain electrode 32. With this structure, the 2DEG concentration in the second 2DEG portion closer to the drain electrode 32 is made higher than the 2DEG concentration in the first 2DEG portion closer to the gate electrode 34. Thus, in an OFF state, an area of the depletion layer as well as a reverse voltage is increased relatively drastically in the area where the first 2DEG portion is formed. Meanwhile, an area of the depletion layer as well as a reverse voltage is increased relatively moderately in the area where the second 2DEG portion is formed. Consequently, while the area where the first 2DEG portion is formed is used to increase the breakdown voltage of the semiconductor device, the area where the second 2DEG portion is formed is used to make the capacitance of the depletion layer in the OFF state change moderately. This prevents occurrence of what is called punch-through and also prevents occurrence of current oscillation.

When the punch-through occurs, electrons are trapped at the portion where the insulating film 20 is disposed between the second nitride semiconductor layer 8 and the drain electrode 32, thereby unfortunately increasing an ON-state resistance. However, the concentration in the second 2DEG portion is increased to prevent the punch-through so that an influence of trapping of electrons can be made relatively small. As a result, the ON-state resistance can be prevented from increasing.

Formation of the second 2DEG portion prevents current oscillation from occurring at the time of switching and prevents the trapping of electrons from increasing ON-state resistance. To further improve such prevention effects, preferably, the distance d₁ between the drain electrode 32 and the gate electrode 34 and the length d₂ of the third nitride semiconductor layer 10 in the direction parallel to the substrate plane have a difference in a range represented by 0.5 μm≤d₁−d₂≤2 μm. Preferably, the thickness t₂ of the third nitride semiconductor layer 10 is 40 nm or less so the concentration in the first 2DEG portion is not made too low.

The structure of the gate electrode 34 is described with reference to FIGS. 1 and 2. However, the structure of the gate electrode 34 is not limited to these examples of the first embodiment. The gate electrode 34 may have, for example, a Schottky structure in which the gate electrode 34 is in direct contact with the second nitride semiconductor layer 8.

This first embodiment can provide a semiconductor device that prevents current oscillation from occurring during switching and prevents the trapping of electrons from increasing ON-state resistance.

Second Embodiment

A semiconductor device according to a second embodiment includes a substrate, a first nitride semiconductor layer disposed on the substrate, a source electrode disposed on the first nitride semiconductor layer, a drain electrode disposed on the first nitride semiconductor layer, a gate electrode disposed between the source electrode and the drain electrode, a second nitride semiconductor layer disposed between the first nitride semiconductor layer and the drain electrode and having a larger bandgap than the first nitride semiconductor layer, a third nitride semiconductor layer disposed on the first nitride semiconductor layer between the gate electrode and the drain electrode and on a side of the second nitride semiconductor layer, the third nitride semiconductor layer having a larger bandgap than the first nitride semiconductor layer and a smaller bandgap than the second nitride semiconductor layer, and a fourth nitride semiconductor layer disposed between the first nitride semiconductor layer and the source electrode and having a larger bandgap than the first nitride semiconductor layer and the third nitride semiconductor layer.

The explanation of aspects of the second embodiment which overlap the first embodiment will not be repeated.

FIG. 3 is a schematic cross-sectional view of a semiconductor device 200 a according to the second embodiment.

A second nitride semiconductor layer 8 a is disposed between the first nitride semiconductor layer 6 and the drain electrode 32 and has a larger bandgap than the first nitride semiconductor layer 6. Specifically, the second nitride semiconductor layer 8 a is made of, for example, undoped Al_(Y)Ga_(1-Y)N (0<Y≤1, X<Y). The second nitride semiconductor layer 8 a has a thickness t₁ of, for example, 15 nm to 50 nm.

To form the second 2DEG portion having a higher concentration than the first 2DEG portion, the second nitride semiconductor layer 8 a may contain silicon (Si) as an n-type impurity.

A third nitride semiconductor layer 8 b is disposed on the first nitride semiconductor layer 6 between the gate electrode 34 and the drain electrode 32 and on a side of the second nitride semiconductor layer 8 a. The third nitride semiconductor layer 8 b has a larger bandgap than the first nitride semiconductor layer 6 and a smaller bandgap than the second nitride semiconductor layer 8 a. Specifically, the third nitride semiconductor layer 8 b is made of, for example, undoped Al_(Z)Ga_(1-Z)N (0<Z≤1, X<Z≤Y). The third nitride semiconductor layer 8 b has a thickness t₃ of, for example, 15 nm to 30 nm. A ratio t₁/t₃ of the thickness t₁ of the second nitride semiconductor layer 8 a to the thickness t₃ of the third nitride semiconductor layer 8 b is in a range of 1 to 1.7. Preferably, the distance d₁ between the drain electrode 32 and the gate electrode 34 and a length d₃ of the third nitride semiconductor layer 8 b in the direction parallel to the substrate plane between the drain electrode 32 and the gate electrode 34 have a difference in a range represented by 0.5 μm≤d₁−d₃≤2 μm.

A fourth nitride semiconductor layer 8 c is disposed between the first nitride semiconductor layer 6 and the source electrode 30 and has a larger bandgap than the first nitride semiconductor layer 6 and the third nitride semiconductor layer 8 b.

Specifically, the fourth nitride semiconductor layer 8 c is made of, for example, undoped Al_(Y)Ga_(1-Y)N (0<Y≤1, X<Y).

FIG. 4 is a schematic cross-sectional view of a semiconductor device 200 b according to another example of the second embodiment. The semiconductor device 200 b is substantially the same as the semiconductor device 200 a illustrated in FIG. 3 except for a structure of the gate electrode 34 and surrounding elements that is similar to the structure illustrated in FIG. 2.

In a similar manner to the first embodiment, the first 2DEG portion is formed in the vicinity of an interface between the first nitride semiconductor layer 6 and the third nitride semiconductor layer 8 b under the third nitride semiconductor layer 8 b. The second 2DEG portion having a relatively high 2DEG concentration is formed in the vicinity of an interface between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8 a under the second nitride semiconductor layer 8 a. Consequently, in a similar manner to the first embodiment, the second embodiment can provide the semiconductor device that prevents current oscillation from occurring during switching and prevents the trapping of electrons from increasing ON-state resistance.

Formation of the first 2DEG portion prevents current oscillation from occurring during switching and prevents the trapping of electrons from increasing ON-state resistance. To further improve such preventive effects, the second 2DEG portion preferably has a higher concentration than the first 2DEG portion. The third nitride semiconductor layer 8 b preferably has a composition represented by Al_(Z)Ga_(1-Z)N (0<Z≤1, X<Z≤Y). The thickness t₃ of the third nitride semiconductor layer 8 b is preferably in a range of 15 nm to 30 nm. A ratio t₁/t₃ of the thickness t₁ of the second nitride semiconductor layer 8 a to the thickness t₃ of the third nitride semiconductor layer 8 b is preferably in a range of 1 to 1.7. Preferably, the distance d₁ between the drain electrode 32 and the gate electrode 34 and the length d₃ of the third nitride semiconductor layer in the direction parallel to the substrate plane between the drain electrode 32 and the gate electrode 34 have a difference in a range represented by 0.5 μm≤d₁−d₃≤2 μm.

This second embodiment can provide a semiconductor device that prevents current oscillation from occurring during switching and prevents the trapping of electrons from increasing ON-state resistance.

Third Embodiment

A semiconductor device according to a third embodiment includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer, a source electrode disposed on the second nitride semiconductor layer, a drain electrode disposed on the second nitride semiconductor layer, a gate electrode disposed between the source electrode and the drain electrode, and a halogen-containing nitride semiconductor layer (the third nitride semiconductor layer) disposed in the second nitride semiconductor layer between the drain electrode and the gate electrode and disposed on a surface of the second nitride semiconductor layer while spaced from the drain electrode, the halogen-containing nitride semiconductor layer containing a halogen group element.

The description aspects of the third embodiment which overlap the first and second embodiments will not be repeated.

FIG. 5 is a schematic cross-sectional view of a semiconductor device 300 a according to the third embodiment.

A halogen-containing nitride semiconductor layer 12 is disposed in the second nitride semiconductor layer 8 between the drain electrode 32 and the gate electrode 34 and disposed on a surface of the second nitride semiconductor layer 8 while being spaced from the drain electrode 32. The halogen-containing nitride semiconductor layer 12 contains a halogen group element. Here, the halogen group element is fluorine (F), chlorine (Cl), bromine (Br), or iodine (I). The halogen-containing nitride semiconductor layer 12 in this third embodiment is formed by ion implantation of the halogen group element or by performing selective epitaxial growth in an atmosphere containing the halogen group element, and subsequently performing thermal posttreatment.

Preferably, a concentration of the halogen group element in the halogen-containing nitride semiconductor layer 12 is 1×10¹² cm⁻² or more and 1×10¹³ cm⁻² or less. A ratio t₁/t₄ for the thickness t₁ of the second nitride semiconductor layer 8 to a thickness t₄ of the halogen-containing nitride semiconductor layer 12 is preferably in a range of 1.5 to and 10. Preferably, the distance d₁ between the drain electrode 32 and the gate electrode 34 and a length d₄ of the halogen-containing nitride semiconductor layer 12 in the direction parallel to the substrate plane have a difference in a range represented by 0.5 μm≤d₁−d₄≤2 μm.

FIG. 6 is a schematic cross-sectional view of a semiconductor device 300 b according to another example of the third embodiment. The semiconductor device 300 b is substantially the same as the semiconductor device 300 a illustrated in FIG. 5 except for a structure of the gate electrode 34 and surrounding elements that is similar to the structure of the semiconductor device 100 b illustrated in FIG. 2 and the structure of the semiconductor device 200 b illustrated in FIG. 4.

The halogen-containing nitride semiconductor layer 12 is provided to form the first 2DEG portion, which has a lower 2DEG concentration than the second 2DEG portion, in the vicinity of an interface between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8 below the halogen-containing nitride semiconductor layer 12. In a similar manner to the first and second embodiments, the third embodiment can provide the semiconductor device that prevents current oscillation from occurring during switching and prevents the trapping of electrons from increasing ON-state resistance.

To form the halogen-containing nitride semiconductor layer 12, there is no need to particularly form a nitride semiconductor layer containing a p-type impurity anew nor to perform selective epitaxial growth to form a stepped portion of a nitride semiconductor layer on the first nitride semiconductor layer 6. In this respect, the semiconductor devices 300 a and 300 b according to this embodiment are produced relatively easily.

Formation of the first 2DEG portion prevents current oscillation from occurring during switching and prevents trapping of electrons from increasing ON-state resistance. In order to further improve such preventive effects, a concentration of the halogen group element in the halogen-containing nitride semiconductor layer 12 is preferably 1×10¹² cm⁻² or more and 1×10¹³ cm⁻² or less. A ratio t₁/t₄ of the thickness t₁ of the second nitride semiconductor layer 8 to a thickness t₄ of the halogen-containing nitride semiconductor layer 12 is preferably in a range of 1.5 to 10. Preferably, the distance d₁ between the drain electrode 32 and the gate electrode 34 and a length d₄ of the halogen-containing nitride semiconductor layer 12 in the direction parallel to the substrate plane have a difference in a range represented by 0.5 μm≤d₁−d₄≤2 μm.

This third embodiment can provide the semiconductor device that prevents current oscillation from occurring during switching and prevents the trapping of electrons from increasing ON-state resistance.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the present disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the embodiments described herein may be made without departing from the spirit of the present disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the present disclosure. 

What is claimed is:
 1. A semiconductor device, comprising: a first nitride semiconductor layer on a substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer; a source electrode on the second nitride semiconductor layer; a drain electrode on the second nitride semiconductor layer; a gate electrode between the source electrode and the drain electrode; and a third nitride semiconductor layer of p-type conductivity on the second nitride semiconductor layer between the drain electrode and the gate electrode and spaced from the drain electrode.
 2. The semiconductor device according claim 1, wherein when a width d₂ of the third nitride semiconductor layer in a direction parallel to a plane of the substrate is subtracted from a shortest distance d₁ between the drain electrode and the gate electrode, the difference is within a range of 0.5 μm to 2 μm, endpoint inclusive.
 3. The semiconductor device according claim 1, wherein a thickness of the third nitride semiconductor layer on the second nitride semiconductor is 40 nm or less.
 4. The semiconductor device according to claim 1, further comprising: an insulating film between the gate electrode and the first nitride semiconductor, between the gate electrode and the second nitride semiconductor, and between the gate electrode and the third nitride semiconductor, a portion of covering the third nitride semiconductor layer such that the third nitride semiconductor layer is between the portion and second nitride semiconductor layer.
 5. The semiconductor device according to claim 1, wherein the gate electrode extends in a trench from an upper surface of the second nitride semiconductor layer into the second nitride semiconductor layer.
 6. The semiconductor device according to claim 1, wherein the third nitride semiconductor layer includes at least one of magnesium, beryllium, carbon, or zinc as a dopant.
 7. The semiconductor device according to claim 1, wherein a first portion of the third nitride semiconductor layer is between the gate electrode and the second nitride semiconductor layer, and a second portion of the third nitride semiconductor layer adjacent to the first portion extends along an upper surface of the second nitride semiconductor to be closer to the drain electrode and a drain-side end portion of the gate electrode.
 8. The semiconductor device according to claim 1, wherein an upper surface of the third nitride semiconductor layer is substantially coplanar with an upper surface of the second nitride semiconductor layer.
 9. The semiconductor device according claim 8, wherein when a width d₂ of the third nitride semiconductor layer in a direction parallel to a plane of the substrate is subtracted from a shortest distance d₁ between the drain electrode and the gate electrode the difference is within a range of 0.5 μm to 2 μm, endpoint inclusive.
 10. The semiconductor device according to claim 1, further comprising: a cap layer of a p-type nitride semiconductor material between the gate electrode and the second nitride semiconductor layer.
 11. The semiconductor device according to claim 10, wherein the third nitride semiconductor layer directly contacts the second nitride semiconductor layer.
 12. The semiconductor device according to claim 1, wherein the third nitride semiconductor layer directly contacts the second nitride semiconductor layer.
 13. A semiconductor device, comprising: a first nitride semiconductor layer on a substrate; a source electrode on the first nitride semiconductor layer; a drain electrode on the first nitride semiconductor layer; a gate electrode between the source electrode and the drain electrode; a second nitride semiconductor layer between the first nitride semiconductor layer and the drain electrode and having a larger bandgap than the first nitride semiconductor layer; a third nitride semiconductor layer directly on the first nitride semiconductor layer, a lateral position of the third nitride semiconductor layer being between a lateral position of a drain-side edge of the gate electrode and a lateral position of a gate-side edge of the drain electrode, a lateral surface of third nitride semiconductor layer directly contacting the second nitride semiconductor layer, the third nitride semiconductor layer having a bandgap larger than the first nitride semiconductor layer and less than or equal to the second nitride semiconductor layer; and a fourth nitride semiconductor layer between the first nitride semiconductor layer and the source electrode and having a larger bandgap than the first nitride semiconductor layer and the third nitride semiconductor layer.
 14. The semiconductor device according claim 13, wherein when a width d₃ of the third nitride semiconductor layer in a direction parallel to a plane of the substrate is subtracted from a shortest distance d₁ between the drain electrode and the gate electrode, the difference is within a range of 0.5 μm to 2 μm, endpoint inclusive.
 15. The semiconductor device according claim 13, wherein a ratio t₁/t₃ for a thickness t₁ of the second nitride semiconductor layer from the first nitride semiconductor layer to an uppermost surface and a thickness t₃ of the third nitride semiconductor layer from the first nitride semiconductor layer to an uppermost surface is between 1 and 1.7, endpoint inclusive.
 16. The semiconductor device according to claim 13, further comprising: a cap layer of a p-type nitride semiconductor material between the gate electrode and the fourth nitride semiconductor layer.
 17. The semiconductor device according to claim 13, wherein the gate electrode is between the third nitride semiconductor layer and the fourth nitride semiconductor layer in a direction substantially parallel to a plane of the substrate.
 18. A semiconductor device, comprising: a first nitride semiconductor layer disposed on a substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer; a source electrode on the second nitride semiconductor layer; a drain electrode on the second nitride semiconductor layer; a gate electrode between the source electrode and the drain electrode; and a third nitride semiconductor layer on the second nitride semiconductor layer, a lateral position of the third nitride semiconductor layer being between a lateral position of a drain-side edge of the gate electrode and a lateral position of a gate-side edge of the drain electrode, third nitride semiconductor layer being spaced from the drain electrode, wherein the third nitride semiconductor layer comprises a halogen group element, and an upper surface of the third nitride semiconductor layer is substantially coplanar with an uppermost surface of the second nitride semiconductor layer.
 19. The semiconductor device according claim 18, wherein a ratio t₁/t₄ for a thickness t₁ of the second nitride semiconductor layer from the first nitride semiconductor layer to the uppermost surface and a thickness t₄ of the third nitride semiconductor layer from the first nitride semiconductor to the upper surface is between 1.5 and 10, endpoint inclusive.
 20. The semiconductor device according to claim 18, further comprising: a cap layer of p-type conductivity between the gate electrode and the uppermost surface of the second nitride semiconductor layer. 